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STA5630
Low power GPS RF front-end
Data brief
Features

Integrated LNA Low power consumption (< 25 mW) 1.8 V supply voltage GPS and Galileo compliant Minimum external components Serial interface 3 bits A/D converter CMOS 65 nm technology 2 kV HBM ESD protected Standard QFN-32 package VFQFPN32
Description
The chip is a fully integrated RF front-end able to down-convert either the GPS L1 signal from 1575.42 MHz to 4.092 MHz. The STA5630 embeds high performance LNA minimizing external component count. The chip uses state of the art CMOS 65 nm technology. A 3-bit ADC converts the IF signal to Sign (SIGN) and Magnitude (MAG0 and MAG1). The magnitude bits are internally integrated in order to control the variable gain amplifiers. The VGA gain can be also set by the SPI interface. Table 1. Device summary
Marking STA5630 STA5630 Package VFQFPN32 VFQFPN32 Packing Tray Tape and reel
The STA5630 accepts a range of reference clocks (10 to 52 MHz) and generates a 16.368 MHz sampling clock (GPS_CLK) for the baseband. The STA5630 embeds LDO to supply the internal core of the device facilitating requirements to external power supply. High performance low power and cost effective device, the STA5630 is the ideal solution for automotive, cellular and consumer battery powered applications.
Order code STA5630 STA5630TR
July 2009
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For further information contact your local STMicroelectronics sales office.
Contents
STA5630
Contents
1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 3 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
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Applications
1
Applications
Three main applications cases are considered and described hereafter. The first uses a passive antenna and only a single RF SAW in front of the internal LNA. It targets low cost and medium performance applications. In this case LNA is ON and RFA is set at minimum gain. The second uses a passive antenna and two RF SAWs. It maximizes the performances in presence of severe blockers. In this case LNA is ON and RFA is set at maximum gain. The third case uses an active antenna. This solution targets applications where the GPS antenna is far from the RF front-end. In this case the signal can be fed into either LNA or RFA input depending on the application conditions. STA5630 is suitable for baseband requiring 16.368/4.092 clock/RF interface and one, two or three bits samples. It accepts reference clocks (TCXO) in the range of 10-52 MHz and delivers a TCXO buffered copy to the baseband. The STA5630 has two default modes selectable by an external pin (MODE):

MODE 0: the chip is configured to use 16.368 MHz as reference frequency, MODE 1: the chip is configured to use 26 MHz as reference frequency.
Other modes are programmed through the serial interface
1.1
Block diagram
Figure 1. Block diagram
LNA_OUT RFA_IN Image Rejection Mixer LNA_EN RFA TP_IF_P TP_IF_N
F_IF = 4.092 MHz
Complex IF filter VGA ADC AGC Selectable BW GPS BW = 2MHz GALILEO BW = 4MHz 3 bits MAG1
SIGN MAG1 MAG0
LNA_IN
LNA Buffer
Digital Integrator
V18_IN
/2
CP
PFD GPS_CLK
V12_OUT V12_RFOUT
LDO
F_LO = 3142.656 MHz
/R 1 / 63 /N 56 / 2047
SPI_NCS SPI_CLK SPI_DI SPI_DO Digital Interface
/48 or / 96 TCXO_CLK
Default Mode Selector MODE0: TCXO=16.368 MHz MODE1: TCXO=26 MHz
CHIP_EN RF_EN MODE
V18_IO
TCXO
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Pin description
STA5630
2
Table 2.
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 EP
Pin description
Pin list description
Pin name TP_IF_P V12_RFA RFA_IN V12_IF V12_OUT V12_RF_OUT V18_IN V12_LNA LNA_OUT GND LNA_IN GND CHIP_EN MODE V18_IO GPS_CLK MAG0 MAG1 SIGN SPI_CLK SPI_NCS SPI_DI SPI_DO TCXO_CLK V12_IO GND_IO TCXO_IN V12_DIG V12_VCO V12_ADC V12_MIX TP_IF_N GND Description RF/IF receiver chain test positive output RF amplifier (RFA) power supply (1.2V) RFA input, DC coupled IF section power supply (1.2V) LDO IF/DIG output. Power supply (1.2V) delivered for IF/ADC/DIG_TCXO/VCO/VDD_IO VCC LDO RF output: Power supply (1.2V) delivered for LNA/RFA/MIXER VCC LDOs power supply (1.8V) Low noise amplifier (LNA) power supply (1.2V) LNA output Ground LNA input, DC coupled Ground Chip Enable Power-On Default Configuration Selector I/Os power supply (1.8V) GPS clock (16.368MHz) Mag0 data (Last significant bit) Mag1 data Sign data (most significant bit) Serial Parallel Interface Clock Serial Parallel Interface Chip Select (Active Low - 1.8V domain) Serial Parallel Interface Data Input Serial Parallel Interface Data Output TCXO Buffered Output Power supply for I/Os digital section (1.2V) I/Os Ground TCXO Input, DC coupled Digital section and TCXO buffer input power supply (1.2V) VCO power supply (1.2V) ADC section power supply (1.2V) Mixer power supply (1.2V) RF/IF receiver chain test negative output Ground Type Analog output Supply pin Analog input Supply pin Output Output Supply pin Supply pin Analog output Ground Analog input Ground Digital input Digital input Supply pin Digital output Digital output Digital output Digital output Digital input Digital input Digital input Digital output Digital output Supply pin Ground Analog input Supply pin Supply pin Supply pin Supply pin Analog output Ground
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Package information
3
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 2.
DIM. MIN. A A A1 A3 b D D2 E E2 e L ddd 0.300 0.180 4.850 3.500 4.850 3.500 0.800 0.800 TYP. 0.900 0.900 0.020 0.200 0.250 5.000 3.600 5.000 3.600 0.500 0.400 MAX. 1.000 MIN. 0.031 TYP. 0.035 MAX. 0.039
VFQFPN32 (5x5x1.0 mm) mechanical data and package dimensions
mm inch
OUTLINE AND MECHANICAL DATA
1.000 0.0315 0.0354 0.0394 0.050 0.0008 0.0020 0.0079 0.300 0.0071 0.0098 0.0118 5.150 0.1909 0.1969 0.2028 3.700 0.1378 0.1417 0.1457 5.150 0.1909 0.1969 0.2028 3.700 0.1378 0.1417 0.1457 0.0197 0.500 0.0118 0.0157 0.0197 0.050 0.0020
VFQFPN32 (5x5x1.0mm) Very Fine Quad Flat Package No lead
7376875 F
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Revision history
STA5630
4
Revision history
Table 3.
Date 22-Jul-2009
Document revision history
Revision 1 Initial release. Changes
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